Syllabus - 3rd Semester - Logic Design - Subject Code - 06ES33

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Syllabus - 3rd Semester - Logic Design - Subject Code - 06ES33

Post by Admin on Thu Aug 05, 2010 6:01 pm

Logic Design

UNIT 1:
Principles of combinational logic-1:
Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3, 4 and 5 variables, Incompletely specified functions (Don’t Care terms), Simplifying Max term equations.
[(Text book 1) 3.1, 3.2, 3.3, 3.4]
7 Hours

UNIT 2:
Principles of combinational Logic-2:
Quine-McCluskey minimization technique- Quine-McCluskey using don’t care terms, Reduced Prime Implicant Tables, Map entered variables [(Text book 1) 3.5, 3.6]
7 Hours

UNIT 3:
Analysis and design of combinational logic - I:
General approach, Decoders-BCD decoders, Encoders.
[(Text book 1) 4.1, 4.3, 4.4]
6 Hours

UNIT 4:
Analysis and design of combinational logic - II:
Digital multiplexers- Using multiplexers as Boolean function generators. Adders and subtractors-Cascading full adders, Look ahead carry,
Binary comparators.
[(Text book 1) 4.5, 4.6 - 4.6.1, 4.6.2, 4.7]
6 Hours

PART –B

UNIT 5:
Sequential Circuits – 1:
Basic Bistable Element, Latches, SR Latch, Application of SR Latch, A Switch Debouncer, The Latch, The gated SR Latch, The gated D Latch, The Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops): The Master-Slave SR Flip-Flops, The Master-Slave JK Flip-Flop, Edge Triggered Flip-Flop: The Positive Edge-Triggered D Flip-Flop, Negative-Edge Triggered D Flip-Flop.
[(Text book 2) 6.1, 6.2, 6.4, 6.5]
7 Hours

UNIT 6:
Sequential Circuits – 2:
Characteristic Equations, Registers, Counters - Binary Ripple Counters, Synchronous Binary counters, Counters based on Shift Registers, Design of a Synchronous counters, Design of a Synchronous Mod-6 Counter using clocked JK Flip-Flops Design of a Synchronous Mod-6 Counter using clocked D, T, or SR Flip-Flops
[(Text book 2) 6.6, 6.7, 6.8, 6.9 – 6.9.1 and 6.9.2]
7 Hours

UNIT 7:
Sequential Design - I:
Introduction, Mealy and Moore Models, State Machine Notation, Synchronous Sequential Circuit Analysis,
[(Text book 1) 6.1, 6.2, 6.3]
6 Hours

UNIT 8:
Sequential Design - II:
Construction of state Diagrams, Counter Design
[(Text book 1) 6.4, 6.5]
6 Hours


TEXT BOOKS:
1. “Digital Logic Applications and Design”, John M Yarbrough, Thomson Learning, 2001.
2. “Digital Principles and Design “, Donald D Givone, Tata McGraw Hill Edition, 2002.

REFERENCE BOOKS:
1. “Fundamentals of logic design”, Charles H Roth, Jr; Thomson Learning, 2004.
2. “Logic and computer design Fundamentals”, Mono and Kim, Pearson, Second edition, 2001.

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